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? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 1 of 14 www.cd4power.com ordering guide summary model v out range i out range v in range ripple/noise ef? ciency lsn2-t/6-w3 0.75-3.3v 0-6a 2.4-5.5v 15mvp-p 94% lsn2-t/6-d12 0.75-5v 0-6a 8.3-14v 15mvp-p 95% lsn2-t/10-w3 0.75-3.3v 0-10a 2.4-5.5v 15mvp-p 95% lsn2-t/10-d12 0.75-5v 0-10a 8.3-14v 30mvp-p 95% lsn2-t/16-w3 0.75-3.3v 0-16a 2.4-5.5v 25mvp-p 95% lsn2-t/16-d12 0.75-5v 0-16a 8.3-14v 30mvp-p 94% mechanical characteristics 6 amp output models 0.50 x 1.00 x 0.275 inches (12.7 x 25.4 x 6.98 mm) 10 & 16 amp models 0.50 x 2.00 x 0.32 inches (12.7 x 50.8 x 8.13 mm) input characteristics parameter typ. @ 25c, full load notes voltage range 2.4-5.5 or 8.3-14v 5v or 12v nominal models current, full power 4.22 to 11.12a model dependent undervoltage shutdown included with autorestart hysteresis short circuit current 60ma output is short circuited remote on/off control positive or negative polarity default polarity is positive output characteristics parameter typ. @ 25c, full load notes voltage 0.75-3.3 or 0.75-5v user adjustable, model dependent current 0-6, 0-10 or 0-16a three ranges, model dependent power dissipation 20, 33, 52w max. three values, model dependent accuracy 2% of v nom 50% load ripple & noise 15-75mvpp model dependent line and load regulation 0.03% overcurrent protection hiccup autorecovery continuous short circuit protection overtemperature protection +115c shutdown ef? ciency (minimum) 92-93% model dependent ef? ciency (typical) 94-95% model dependent general specifications parameter typ. @ 25c, full load notes transient response 25sec 50% load step to 2% of ? nal value operating temperature range C40 to +85c with 200 lfm air? ow safety ul/iec/en 60950 and csa c22.2-no.234 emi fcc pt.15, class b pb lead-free construction/attach features user-selectable outputs: 0.75-5v (d12 models) or 0.75-3.3v (w3 models) 6, 10 or 16a maximum output current double lead free to rohs standards selectable phased start-up sequencing and tracking wide range v in 8.3-14v or 2.4-5.5v up to 52 watts total output power very high ef? ciency up to 95% starts up into pre-biased load fast settling, high di/dt i out slew rate description these miniature point-of-load (pol) switching dc/dc converters are ideal regulation and supply elements for distributed power and intermedi- ate bus architectures. fully compatible with the distributed-power open standards alliance speci? cation (www.dosapower.com), lsn2s can power cpus, programmable logic and mixed- voltage systems with little heat and low noise. a typical application uses a master isolated 12 or 5vdc supply and individual lsn2 converters for local 1.8 and 3.3vdc supplies. all system isolation resides in the central supply, leaving lower cost pol regulation at the load. the lsn2s can deliver very high power (to 52 watts) in a tiny area with- out heat sinking or external components. they feature quick transient response (to 25sec) and very fast current slew rates (to 20a/sec).
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 2 of 14 www.cd4power.com part number structure performance specifications and ordering guide ? model output input ef? ciency package (case/ pinout) v out (volts) i out (amps) power (watts) r/n (mvp-p) ? regulation ? v in nom. (volts) range ? (volts) i in ? (ma/a) typ. max. line load min. typ. lsn2-t/6-w3 0.75-3.3 6 19.8 15 25 0.3% 0.3% 5 2.4-5.5 50/4.22 92% 94% b12, p69 lsn2-t/6-d12 0.75-5 6 19.8 15 25 0.3% 0.3% 12 8.3-14 70/2.69 90% 93% b12, p69 lsn2-t/10-w3 0.75-3.3 10 33.0 15 25 0.3% 0.3% 5 2.4-5.5 50/6.95 93% 95% b11, p68 lsn2-t/10-d12 0.75-5 10 33.0 30 75 0.3% 0.3% 12 8.3-14 100/4.39 93% 95% b11, p68 lsn2-t/16-w3 0.75-3.3 16 52.8 25 50 0.3% 0.3% 5 2.4-5.5 50/11.12 93% 95% b11, p68 lsn2-t/16-d12 ? 0.75-5 16 52.8 30 75 0.3% 0.3% 12 8.3-14 100/7.1 92% 94% b11, p68 maximum rated output current in amps non-isolated smt output con? guration: l = unipolar low voltage nominal output voltage: 0.75-3.3 volts (w3) 0.75-5 volts (d12) l sn2 - / d12 - t 16 n g input voltage range: d12 = 8.3-14 volts (12v nominal) w3 = 2.4-5.5 volts (5v nominal) on/off polarity: blank = positive polarity n = negative polarity power good output: blank = omitted g = installed ? typical at t a = +25c under nominal line voltage and full-load conditions, unless noted. all models are tested and speci? ed with external 22f tantalum input and output capacitors. these capacitors are necessary to accommodate our test equipment and may not be required to achieve speci? ed performance in your applications. see i/o filtering and noise reduction. ? ripple/noise (r/n) is tested/speci? ed over a 20mhz bandwidth and may be reduced with external ? ltering. see i/o filtering and noise reduction for details. ? these devices have no minimum-load requirements and will regulate under no-load conditions. regulation speci? cations describe the output-voltage deviation as the line voltage or load is varied from its nominal/midpoint value to either extreme. ? nominal line voltage, no-load/full-load conditions. ? v in must be 0.5v greater than v out . ? lsn2-txx-d12 ef? ciencies are shown at 5v out . note: not all model number combinations are available. contact c&d technologies (datel). c rohs-6 compliant* - *contact c&d technologies (datel) for availability.
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 3 of 14 www.cd4power.com performance/functional speci? cations (1) input input voltage range see ordering guide isolation not isolated, input and output commons are internally connected start-up threshold w3 models 2.2 volts 12v models 8 volts undervoltage shutdown w3 models 2.0 volts 12v models 7.5 volts overvoltage shutdown none re? ected (back) ripple current (2) 10-70map-p (model dependent) internal input filter type capacitive reverse polarity protection see fuse information input current: full load conditions see ordering guide inrush transient 0.1a 2 sec shutdown mode (off, uv, ot) 5ma output short circuit 60ma no load w3 models 50ma 12v models 100ma low line (v in = v min ) lsn2-t/6-w3 5.54 amps lsn2-t/6-d12 3.85 amps lsn2-t/10-w3 9.14 amps lsn2-t/10-d12 6.31 amps lsn2-t/16-w3 14.63 amps lsn2-t/16-d12 10.2 amps remote on/off control: (5) positive logic (no model suf? x) off = ground pin to +0.8v max. on = open pin or +2.5v min. to +v in max. negative logic (n model suf? x) on = open pin to +0.3v max. off = +2.5v min. to +v in max. current 1ma max. output voltage output range see ordering guide minimum loading no minimum load accuracy (50% load) 2% of v nom voltage adjustment range (13) see ordering guide temperature coef? cient 0.02% of v out range per c ripple/noise (20 mhz bandwidth) see ordering guide and (8) line/load regulation (see tech notes) see ordering guide and (10) ef? ciency see ordering guide maximum capacitive loading: (15) lsn2-t/6 models: cap-esr = 0.001 to 0.01 3000f cap-esr >0.01 5000f lsn2-t/10 and -t/16 models: cap-esr = 0.001 to 0.01 5000f cap-esr >0.01 10,000f current limit inception: (98% of v out ) lsn2-t/6 models 11-13 amps (cold startup) 11 amps (after warm up) lsn2-t/10 models 18.75 amps (cold startup) 16.75 amps (after warm up) lsn2-t/16 models 24 amps (cold startup) 21 amps (after warm up) short circuit mode (6) short circuit current output 600ma protection method (17) hiccup autorecovery on overload removal short circuit duration continuous, no damage (output shorted to ground) prebias startup (16) converter will start up if the external output voltage is less than v nom sequencing slew rate 2v max. per millisecond startup delay until sequence start 10 milliseconds tracking accuracy, rising input v out = 100mv of sequence in tracking accuracy, falling input v out = 200mv of sequence in sequence pin input impedance 400k to 1m remote sense to v out 0.5v max. (7) power good output (14) true (ok) = open drain (g suf? x) false (not ok) = signal ground to 0.4v power_good con? guration mosfet to ground with external user pullup, 10ma max. sink dynamic characteristics dynamic load response 25sec to 2% of ? nal value (50-100-50% load step, di/dt = 20a/msec) start-up time 4-7msec for v out = nominal (v in on to v out regulated or on/off to v out ) switching frequency lsn2-t/6 models 315khz lsn2-t/10 and -t/16 models 230khz environmental calculated mtbf (4) tbc hours operating temperature range (ambient) no derating, natural convection C40 to +63c, vertical mount, 2.5v out (9) with derating see derating curves operating pc board temperature C40 to +100c max. (12) storage temperature range C55 to +125c thermal protection/shutdown +115c density altitude 0 to 10,000 feet relative humidity 10% to 90%, non-condensing physical outline dimensions see mechanical speci? cations removable heat shield nylon 46 weight 0.28 ounces (7.8 grams) electromagnetic interference fcc part 15, class b, en55022 (may (conducted and radiated) need external ? lter) safety ul/cul 60950 csa-c22.2 no.234 iec/en 60950 flammability rating ul94v-0 absolute maximum ratings input voltage (continuous or transient) w3 models +7 volts 12v models +15 volts on/off control C0.3v min. to +v in max. input reverse polarity protection see fuse section output current (7) current-limited. devices can withstand sustained short circuit without damage. storage temperature C55 to +125c lead temperature (soldering 10 sec. max.) +280c these are stress ratings. exposure of devices to any of these conditions may adversely affect long-term reliability. proper operation under conditions other than those listed in the perfor- mance/functional speci? cations table is not implied.
figure 1. lsn2 series simpli ed schematic ? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 4 of 14 www.cd4power.com performance/functional speci? cation notes: (1) all models are tested and speci? ed with external 1 || 10f ceramic/tantalum output capacitors and a 22f external input capacitor. all capacitors are low esr types. these capacitors are necessary to accommodate our test equipment and may not be required to achieve speci? ed performance in your applications. all models are stable and regulate within spec under no-load conditions. general conditions for speci? cations are +25c, v in = nominal, v out = nominal, full load. nomi- nal output voltage is +5v for d12 models and +3.3v for w3 models. (2) input back ripple current is tested and speci? ed over a 5-20mhz bandwidth. input ? ltering is c in = 2 x 100f tantalum, c bus = 1000f electrolytic, l bus = 1h. (3) note that maximum power derating curves indicate an average current at nominal input voltage. at higher temperatures and/or lower air? ow, the dc/dc converter will tolerate brief full current outputs if the total rms current over time does not exceed the derating curve. (4) mean time before failure is calculated using the telcordia (belcore) sr-332 method 1, case 3, ground ? xed conditions, t pcboard = +25c, full output load, natural air convection. (5) the on/off control may be driven with external logic or by applying appropriate external voltages which are referenced to Cinput common. the on/off control input should use either an open collector/open drain transistor or logic gate which does not exceed +v in . a 68k external pullup resistor to +v in will cause the on state for negative logic models. (6) short circuit shutdown begins when the output voltage under increasing load degrades approxi- mately 2% from the selected setting. (7) if sense is connected remotely at the load, up to 0.5 volts difference is allowed between the sense and +v out pins to compensate for ohmic voltage drop in the power lines. a larger voltage drop may cause the converter to exceed maximum power dissipation. i/o filtering and noise reduction all models in the lsn2 series are tested and speci? ed with external 1 || 10f ceramic/tantalum output capacitors and a 22f tantalum input capacitor. these capacitors are necessary to accommodate our test equip- ment and may not be required to achieve desired performance in your appli- cation. the lsn2's are designed with high-quality, high-performance internal i/o caps, and will operate within spec in most applications with no additional external components. in particular, the lsn2's input capacitors are speci? ed for low esr and are fully rated to handle the units' input ripple currents. similarly, the internal technical notes (8) output noise may be further reduced by adding an external ? lter. see i/o filtering and noise reduction. (9) all models are fully operational and meet published speci? cations, including cold start at C40c. v out is nominal. (10) regulation speci? cations describe the deviation as the line input voltage or output load current is varied from a nominal midpoint value to either extreme. (11) other input or output voltage ranges are available under scheduled quantity special order. (12) maximum pc board temperature is measured with the sensor in the center. (13) do not exceed maximum power speci? cations when adjusting the output trim. (14) when sequencing is not used, the power good output is true at any time the output is within approximately 10% of the voltage set point. power good basically indicates if the converter is in regulation. power good detects over temperature if the pwm has shut down due to ot. power good does not directly detect over current. if sequencing is in progress, power good will falsely indicate true (valid) before the output reaches its setpoint. ignore power good if sequencing is in transition. (15) the maximum output capacitive loads depend on the the equivalent series resistance (esr) of the external output capacitor. (16) do not use pre-bias startup and sequencing together. see technical notes below. (17) after short circuit shutdown, if the load is partially removed such that the load still exceeds the overcurrent (oc) detection, the converter will remain in hiccup restart mode. (18) for best noise performance, leave the track/sequence pin open when not used. output capacitors are speci? ed for low esr and full-range frequency response. in critical applications, input/output ripple/noise may be further reduced using ? ltering techniques, the simplest being the installation of external i/o caps. external input capacitors serve primarily as energy-storage devices. they minimize high-frequency variations in input voltage (usually caused by ir drops in conductors leading to the dc/dc) as the switching converter draws pulses of current. input capacitors should be selected for bulk capacitance (at appropriate frequencies), low esr, and high rms-ripple-current ratings. the switching nature of modern dc/dc's requires that the dc input voltage source have low ac impedance at the frequencies of interest. highly inductive source impedances can greatly affect system stability. your speci? c system con? guration may necessitate additional considerations. ).054 #/--/. 6 42!#+ ).054 07- #/.42/,,%2 #522%.4 3%.3% 2%&%2%.#% %22/2!-0 6 ## /./&& #/.42/, 6 /54 42)- /54054 7 3%.3% #/--/.
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 5 of 14 www.cd4power.com figure 3. measuring output ripple/noise (pard) # #&#%2!-)# #&4!.4!,5- ,/!$ ).#(%3 mm &2/--/$5,% # 2 ,/!$ #/00%2342)0 #/00%2342)0 3#/0% /54054 #/--/. 3%.3% # ). 6 ). # "53 , "53 # ). x&%32m 7 k(z # "53 &%32m 7 k(z , "53 ( ).054 #/--/. #522%.4 02/"% 4/ /3#),,/3#/0% n figure 2. measuring input ripple current output ripple/noise (also referred to as periodic and random deviations or pard) may be reduced below speci? ed limits with the installation of additional external output capacitors. output capacitors function as true ? lter elements and should be selected for bulk capacitance, low esr, and appropriate fre- quency response. any scope measurements of pard should be made directly at the dc/dc output pins with scope probe ground less than 0.5" in length. all external capacitors should have appropriate voltage ratings and be located as close to the converters as possible. temperature variations for all relevant parameters should be taken into consideration. the most effective combinat ion of external i/o capacitors will be a function of your line voltage and source impedance, as well as your particular load and layout conditions. our appl ications engineers can recommend potential solutions and discuss the possibility of our modifying a given devices internal ? ltering to meet your speci? c requireme nts. contact our applications engineer- ing group for additional details. input fusing most applications and or safety agencies require the installation of fuses at the inputs of power conversion components. the lsn2 series are not inter- nally fused. therefore, if input fusing is mandatory, either a normal-blow or a slow-blow fuse with a value no greater than twice the maximum input current calculated at low line with the converter's minimum ef? ciency should be installed within the ungrounded input path to the converter. safety considerations lsn2 sips are non-isolated dc/dc converters. in general, all dc/dc's must be installed, including considerations for i/o voltages and spacing/sepa- ration requirements, in compliance with relevant safety-agency speci- ? cations (usually ul/iec/en60950). in particular, for a non-isolated converter's output voltage to meet selv (safety extra low voltage) requirements, its input must be selv compliant. if the output needs to be elv (extra low voltage), the input must be elv. input overvoltage and reverse-polarity protection lsn2 sip series dc/dc's do not incorporate either input overvoltage or input reverse-polarity protection. input voltages in excess of the speci? ed absolute maximum ratings and input polarity reversals of longer than "instantaneous" duration can cause permanent damage to these devices. start-up time the v in to v out start-up time is the interval between the time at which a ramping input voltage crosses the lower limit of the speci? ed input volt- age range and the fully loaded output voltage enters and remains within its speci? ed accuracy band. actual measured times will vary with input source impedance, external input capacitance, and the slew rate and ? nal value of the input voltage as it appears to the converter. the on/off to v out start-up time assumes the converter is turned off via the on/off control with the nominal input voltage already applied to the converter. the speci? cation de? nes the interval between the time at which the converter is turned on and the fully loaded output voltage enters and remains within its speci? ed accuracy band. see typical performance curves. remote sense lsn2 series offer an output sense function. the sense function enables point- of-use regulation for overcoming moderate ir drops in conductors and/or cabling. since these are non-isolated devices whose inputs and outputs usu- ally share the same ground plane, sense is provided only for the +output. the remote sense line is part of the feedback control loop regulating the dc/dc converters output. the sense line carries very little current and consequently requires a minimal cross-sectional-area conductor. as such, it is not a low-impedance point and must be treated with care in layout and cabling. sense lines should be run adjacent to signals (preferably ground), and in cable and/or discrete-wiring applications, twisted-pair or similar techniques should be used. to prevent high frequency voltage differences between v out and sense, we recommend installation of a 1000pf capacitor close to the converter. the sense function is capable of compensating for voltage drops between the +output and +sense pins that do not exceed 10% of v out . [v out (+) C common] C [sense(+) C common] 10%v out power derating (output current limiting) is based upon maximum output current and voltage at the converter's output pins. use of trim and sense functions can cause the output voltage to increase, thereby increasing output power beyond the lsn2's speci? ed rating. therefore: (v out at pins) x (i out ) rated output power
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 6 of 14 www.cd4power.com figure 5. inverting on/off control ).054 6 #/.42/,,%2 3(54$/7. 3)'.!, '2/5.$ #/--/. /./&& #/.42/, %84%2.!, /0%. #/,,%#4/2 ).054 k 7 figure 4. on/off control using an external open collector driver ).054 6 #/.42/,,%2 ()/&& ,//. 3-!,, 3)'.!, 42!.3)34/2 3(54$/7. 3)'.!, '2/5.$ #/--/. /./&& #/.42/, the internal 10.5 resistor between +sense and +output (see figure 1) serves to protect the sense function by limiting the output current ? owing through the sense line if the main output is disconnected. it also prevents output voltage runaway if the sense connection is disconnected. note: if the sense function is not used for remote regulation, +sense must be tied to +output at the dc/dc converter pins. remote on/off control the input-side remote on/off control is an external input signal available in either positive (no suf? x) or negative (n suf? x) polarity. normally this input is controlled by the users external transistor or relay. with simple external circuits, it may also be selected by logic outputs. please note however that the actual control threshold levels vary somewhat with the pwm supply and therefore are best suited to open collector or open drain type logic. the on/off control takes effect only when appropriate input power has been applied and stabilized (approximately 7msec). for positive polarity, the default operation leaves this pin open (unconnected) or high. the output will then always be on (enabled) whenever appropriate input power is applied. negative polarity models require the on/off to be grounded to the Cinput terminal or brought low to turn the converter on. to turn the converter off, for positive polarity models, ground the on/off control or bring it low. for negative polarity, raise the on/off at least to +2.5v to turn it off. dynamic control of the on/off must be capable of sinking or sourcing the control current (approximately 1ma max.) and not overdrive the input greater than the +v in power input. always wait for the input power to stabilize before activating the on/off control. be aware that a delay of several milliseconds occurs (see speci? cations) between activation of the control and the resulting change in the output. power-up sequencing if a controlled start-up of one or more lsn2 series dc/dc converters is required, or if several output voltages need to be powered-up in a given sequence, the on/off control pin can be driven with an external open collector device as per figure 4. leaving the input of the on/off circuit closed during power-up will have the output of the dc/dc converter disabled. when the input to the external open collector is pulled high, the dc/dc converter's output will be enabled. output overvoltage protection lsn2 sip series dc/dc converters do not incorporate output overvoltage pro- tection. in the extremely rare situation in which the devices feedback loop is broken, the output voltage may run to excessively high levels (v out = v in ). if it is absolutely imperative that you protect your load against any and all possible overvoltage situations, voltage limiting circuitry must be provided external to the power converter. output overcurrent detection overloading the power converter's output for an extended time will invariably cause internal component temperatures to exceed their maximum ratings and eventually lead to component failure. high-current-carrying components such as inductors, fet's and diodes are at the highest risk. lsn2 sip series dc/dc converters incorporate an output overcurrent detection and shutdown function that serves to protect both the power converter and its load. if the output current exceeds it maximum rating by typically 50% or if the output voltage drops to less than 98% of it original value, the lsn2's internal overcurrent-detection circuitry immediately turns off the converter, which then goes into a "hiccup" mode. while hiccupping, the converter will continuously attempt to restart itself, go into overcurrent, and then shut down. once the output short is removed, the converter will automatically restart itself. output reverse conduction many dc/dc's using synchronous recti? cation suffer from output reverse conduction. if those devices have a voltage applied across their output before a voltage is applied to their input (this typically occurs when another power supply starts before them in a power-sequenced application), they will either fail to start or self destruct. in both cases, the cause is the "freewheeling" or "catch" fet biasing itself on and effectively becoming a short circuit. lsn2 sip dc/dc converters do not suffer from output reverse conduction. they employ proprietary gate drive circuitry that makes them immune to moderate applied output overvoltages. thermal considerations and thermal protection the typical output-current thermal-derating curves shown below enable designers to determine how much current they can reliably derive from each model of the lsn2 sips under known ambient-temperature and air-? ow con- ditions. similarly, the curves indicate how much air ? ow is required to reliably deliver a speci? c output current at known temperatures.
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 7 of 14 www.cd4power.com solutions to improve start up, review the conditions above. one of the better solutions is to place a moderate size capacitor very close to the input terminals. you may need two parallel capacitors. a larger electrolytic or tantalum cap sup- plies the surge current and a smaller parallel low-esr ceramic cap gives low ac impedance. too large an electrolytic capacitor may have higher internal impedance (esr) and/or lower the start up slew rate enough to upset the dc/dcs controller. make sure the capacitors can tolerate re? ected switching current pulses from the converter. the capacitors will not help if the input source has poor regulation. a con- verter which starts successfully at 3.3 volts will turn off if the input voltage decays to below the input voltage theshold, regardless of external capaci- tance. increase the input start up voltage if possible to raise the downward voltage spike. also, make sure that the input voltage ramps up in a reasonably short time (less than a few milliseconds). if possible, move the input source closer to the converter to reduce ohmic losses in the input wiring. remember that the input current is carried both by the wiring and the ground plane return. make sure the ground plane uses adequate thickness copper. run additional bus wire if necessary. any added output capacitor should use just enough capacitance (and no more) to reduce output noise at the load and to avoid marginal threshold noise prob- lems with external logic. an output cap will also decouple inductive reac- tance in the load. certain kinds of electronic loads include constant current characteristics which destabilize the output with insuf? cient capacitance. if the wiring to the eventual load is long, consider placing this decoupling cap at the load. use the remote sense input to avoid ohmic voltage drop errors. an elegant solution to start up problems is to apply the input voltage with the remote on/off control ? rst in the off setting (for those converters with an on/ off control). after the speci? ed start-up delay (usually under 20 msec), turn on the converter. the controller will have already been stabilized. the short delay will not be noticed in most applications. be aware of applications which need power management (phased start up). finally, it is challenging to model some application circuits with absolute ? del- ity. how low is the resistance of your ground plane? what is the inductance (and distributed capacitance) of external wiring? even a detailed mathemati- cal model may not get all aspects of your circuit. therefore it is dif? cult to give cap values which serve all applications. some experimentation may be required. pre-biased startup newer systems with multiple power voltages have an additional problem besides startup sequencing. some sections have power already partially applied (possibly because of earlier power sequencing) or have leakage power present so that the dc/dc converter must power up into an existing voltage. this power may either be stored in an external bypass capacitor or supplied by an active source. this pre-biased condition can also occur with some types of program- mable logic or because of blocking diode leakage or small currents passed through forward biased esd diodes. conventional dc/dcs may fail to start up correctly if there is output voltage already present. and some external circuits are adversely affected when the low side mosfet in a synchronous recti? er converter sinks current at start up. the highest temperatures in lsn2 sips occur at their output inductor, whose heat is generated primarily by i 2 r losses. the derating curves were developed using thermocouples to monitor the inductor temperature and varying the load to keep that temperature below +110c under the assorted conditions of air ? ow and air temperature. once the temperature exceeds +115c (approx.), the thermal protection will disable the converter. automatic restart occurs after the temperature has dropped below +110c. as you may deduce from the derating curves and observe in the ef? ciency curves on the following pages, lsn2 sips maintain virtually constant ef? ciency from half to full load, and consequently deliver very impressive temperature performance even if operating at full load. lastly, when lsn2 sips are installed in system boards, they are obviously subject to numerous factors and tolerances not taken into account here. if you are attempting to extract the most current out of these units under demand- ing temperature conditions, we advise you to monitor the output-inductor temperature to ensure it remains below +110c at all times. start up considerations when power is ? rst applied to the dc/dc converter, operation is different than when the converter is running and stabilized. there is some risk of start up dif? culties if you do not observe several application features. lower output voltage converters may have more problems here since they tend to have higher output currents. operation is most critical with any combination of the following external factors: 1 - low initial input line voltage and/or poor regulation of the input source. 2 C full output load current on lower output voltage converters. 3 C slow slew rate of input voltage. 4 C longer distance to input voltage source and/or higher external input source impedance. 5 - limited or insuf? cient ground plane. external wiring that is too small. 6 C too small external input capacitance. too high esr. 7 C high output capacitance causing a start up charge overcurrent surge. 8 C output loads with excessive inductive reactance or constant current characteristics. if the input voltage is already at the low limit before power is applied, the start up surge current may instantaneously reduce the voltage at the input terminals to below the speci? ed minimum voltage. even if this voltage depres- sion is very brief, this may interfere with the on-board controller and possibly cause a failed start. or the converter may start but the input current load will now drive the input voltage below its running low limit and the converter will shut down. if you measure the input voltage before start up with a digital voltmeter (dvm), the voltage may appear to be adequate. limited external capacitance and/or too high a source impedance may cause a short downward spike at power up, causing an instantaneous voltage drop. use an oscilloscope not a dvm to observe this spike. the converters soft-start controller is sensitive to input voltage. what matters here is the actual voltage at the input terminals at all times. symptoms of start-up dif? culties may include failed started, output oscillation or brief start up then overcurrent shutdown. since the input voltage is never absolutely constant, the converter may start up at some times and not at others.
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 8 of 14 www.cd4power.com r trim ( ) = _____________ ?5110 v o ? 0.7525 21070 r trim ( ) = _____________ ?1000 v o ? 0.7525 10500 the lsn2 series includes a pre-bias startup mode to prevent these initializa- tion problems. essentially, the converter acts as a simple buck converter until the output reaches its set point voltage at which time it converts to a synchro- nous recti? er design. this feature is variously called monotonic because the voltage does not decay (from low side mosfet shorting) or produce a negative transient once the input power is applied and the startup sequence begins. dont use pre-biasing and sequencing together normally, you would use startup sequencing on multiple dc/dcs to solve the pre-bias problem. by causing all power sources to ramp up together, no one source can dominate and force the others to fail to start. for most applica- tions, do not use startup sequencing in a pre-bias application, especially with an external active power source. if you have active source pre-biasing, leave the sequence input open so that the output will step up quickly and safely. a symptom of this condition is repeated failed starts. you can further verify this by removing the existing load and testing it with a separate passive resistive load which does not exceed full current. if the resistive load starts successfully, you may be trying to drive an external pre-biased active source. it may also be possible to use pre-bias and sequencing together if the pre- bias source is in fact only a small external bypass capacitor slowly charged by leakage currents. test your application to be sure. output adjustments the lsn2 series includes a special output voltage trimming feature which is fully compatible with competitive units. the output voltage may be varied using a single trim resistor from the trim input to power common (pin 4) or an external dc trim voltage applied between the trim input and power common. the output voltage range for w3 models is 0.75 to 3.3 volts. for d12 models, the output range is 0.75 to 5 volts. important: on w3 models only, for outputs greater than 3 volts up to 3.3 volts maximum, the input supply must be 4.5 volts minimum. to retain proper regulation, do not exceed the 3.3v output. as with other trim adjustments, be sure to use a precision low-tempco resis- tor (100 ppm/c) mounted close to the converter with short leads. also be aware that the output voltage accuracy is 2% (typical) therefore you may need to vary this resistance slightly to achieve your desired output setting. two different trim equations are used for the w3 and d12 models. w3 models resistor trim equation: the w3 models ? xed trim resistors to set the output voltage are: v out (typ.) 0.7525v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v r trim (k ) open 80.021 41.973 23.077 15.004 6.947 3.16 d12 models resistor trim equation: v out 0.7525v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5v r trim (k ) open 41.424 22.46 13.05 9.024 5.009 3.122 1.472 voltage trim the lsn2 series may also be trimmed using an external voltage applied between the trim input and output common. be aware that the internal load impedance looking into trim pin is approximately 5k . therefore, you may have to compensate for this in the source resistance of your external voltage reference. use a low noise dc reference and short leads. mount the leads close to the converter. consider using a small bypass capacitor (0.1f ceramic) between trim and output common to avoid instability. two different trim equations are used for the w3 and d12 models. w3 models voltage trim equation: v trim (in volts) = 0.7 C(0.1698 x (v o C 0.7525)) the lsn2 w3 ? xed trim voltages to set the output voltage are: v out (typ.) 0.7525v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v v trim open 0.6928v 0.624v 0.5731v 0.5221v 0.4033v 0.267v d12 models voltage trim equation: v trim (in volts) = 0.7 C(0.0667 x (v o C 0.7525)) the lsn2 d12 ? xed trim voltages to set the output voltage are: v out 0.7525v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5v v trim (v) open 0.6835 0.670 0.650 0.630 0.583 0.530 0.4166 2 42)- 6 /54 42)- #/--/. 6 42)- 6 /54 42)- #/--/. n figure 6. trim connections
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 9 of 14 www.cd4power.com lsn2 power sequencing whereas in the old days, one master switch simultaneously turned on the power for all parts of a system, many modern systems require multiple supply voltages for different on-board sections. typically the cpu or microcontroller needs 1.8 volts or lower. memory (particularly ddr) may use 1.8 to 2.5 volts. interface glue and chipset logic might use +3.3vdc power while input/ output subsystems may need +5v. finally, peripherals use 5v and/or 12v. timing is everything this mix of system voltages is being distributed by several local power solu- tions including intermediate bus architecture (iba) bus converters, point-of- load (pol) dc/dc converters and sometimes a linear regulator, all sourced from a master ac power supply. while this mix of voltages is challenging enough, a further dif? culty is the start-up and shutdown timing relationship between these power sources and relative voltage differences between them. for many systems, the cpu and memory must be powered up, boot-strap loaded and stabilized before the i/o section is turned on. this avoids uncom- manded data bytes being transferred, compromising an active external network or placing the i/o section in an unde? ned mode. or it keeps bad com- mands out of disk and peripheral controllers until they are ready to go to work. another goal for staggered power-up is to avoid an oversize load applied to the master source all at once. a more serious reason to manage the timing and voltage differences is to avoid either a latchup condition in program- mable logic (a latchup might ignore commands or would respond improperly to them) or a high current startup situation (which may damage on-board circuits). and on the power down phase, inappropriate timing or voltages can cause interface logic to send a wrong epitaph command. two approaches there are two ways to manage these timing and voltage differences. either the power up/down sequence can be controlled by discrete on/off logic con- trols for each power supply (see figure 7). or the power up/down cycle is set by sequencing or tracking circuits. some systems combine both methods. the ? rst system (discrete on/off controls) applies signals from an already- powered logic sequencer or dedicated microcontroller which turns on each downstream power section in cascaded series. this of course assumes all pols have on/off controls. a distinct advantage of the sequencing controller is that it can produce an all on output signal to state that the full system is stable and ready to go to work. for additional safety, the sequencer can moni- tor the output voltages of all downstream pols with an a/d converter system. however the sequencer controller has some obvious dif? culties besides extra cost, wiring and programming complexity. first, power is applied as a fast-rising, all-or-nothing step which may be unacceptable to certain circuits, especially large output bypass capacitors. these could force pols into overcurrent shutdown. and some circuits (such as many linear regulators and some pols) may not have convenient start-up controls. this requires design- ing and fabricating external power controls such as high-current mosfets. if the power up/down timing needs to be closely controlled, each pol must be characterized for start-up and down times. these often varyone pol may stabilize in 15 milliseconds whereas another takes 50 milliseconds. another problem is that the sequencing controller itself must be already running and stabilized before starting up other circuits. if there is a glitch in the system, the power up/down sequencer could get out of step with possible disastrous results. lastly, changing the timing may require reprogramming the logic sequencer or rewriting software. sequence/track input a different power sequencing solution is employed on datels lsn2 dc/dc converter. after external input power is applied and the converter stabilizes, a high impedance sequence/track input pin accepts an external analog volt- age. the output power voltage will then track this sequence/track input at a one-to-one ratio up to the nominal set point voltage for that converter. this sequencing input may be ramped, delayed, stepped or otherwise phased as needed for the output power, all fully controlled by the users simple external circuits. as a direct input to the converters feedback loop, response to the sequence/track input is very fast (milliseconds). by properly controlling this sequence pin, most operations of the discrete on/off logic sequencer may be duplicated. the sequence pin system does not use the converters enable on/off control (unless it is a master emergency shut down system). power phasing architectures observe the simpli? ed timing diagrams below. there are many possible power phasing architectures and these are just some examples to help you analyze your system. each application will be different. multiple output voltages may require more complex timing than that shown here. "53 #/.6%24%2 3%15%.#).' #/.42/,,%2 %.!",% 6 ). 6 ). 0/, ! h!,,/.v 0/, " #05 6 4//4(%20/,s 6 ,/!$3 6dc 6 ,/!$3 %.!",% 4)-% 3ettling $elay 0/,! %.!",% 34!24503%15%.#% /&& /&& /. /. 0/," figure 7. power up/down sequencing controller
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 10 of 14 www.cd4power.com these diagrams illustrate the time and slew rate relationship between two typical power output voltages. generally the master will be a primary power voltage in the system which must be present ? rst or coincident with any slave power voltages. the master output voltage is connected to the slaves sequence input, either by a voltage divider, divider-plus-capacitor or some other method. several standard sequencing architectures are prevalent. they are concerned with three factors: the time relationship between the master and slave voltages the voltage difference relationship between the master and slave the voltage slew rate (ramp slope) of each converters output. for most systems, the time relationship is the dominant factor. the voltage difference relationship is important for systems very concerned about possible latchup of programmable devices or overdriving esd diodes. lower slew rates avoid overcurrent shutdown during bypass cap charge-up. in figure 18, two pols ramp up at the same rate until they reach their dif- ferent respective ? nal set point voltages. during the ramp, their voltages are nearly identical. this avoids problems with large currents ? owing between figures 10 and 11 show both delayed start up and delayed ? nal voltages for two converters. figure 10 is called inclusive because the later starting pol ? nishes inside the earlier pol. the timing in figure 10 is more easily built using a combined digital sequence controller and the sequence/track pin. figure 11 is the same strategy as figure 10 but with an exclusive timing relationship staggered approximately the same at power-up and power-down. operation to use the sequence pin after power start-up stabilizes, apply a rising external voltage to the sequence input. as the voltage rises, the output voltage will track the sequence input (gain = 1). the output voltage will stop rising when it reaches the normal set point for the converter. the sequence input may optionally continue to rise without any effect on the output. keep the sequence input voltage below the converters input supply voltage. use a similar strategy on power down. the output voltage will stay constant until the sequence input falls below the set point. any strategy may be used to deliver the power up/down ramps. the circuits below show simple rc networks but you may also use operational ampli? ers, d/a converters, etc. circuits the circuits shown in figures 12 through 14 introduce several concepts when using these sequencing controls on point-of-load (pol) converters. these circuits are only for reference and are not intended as ? nal designs ready for your application. also, numerous connections are omitted for clarity. 6 /54 0/,!6 /54 4)-% /54054 6/,4!'% 0/,"6 /54 3taggered 4imes 0/,!6 /54 4)-% /54054 6/,4!'% 0/,"6 /54 #oincident 6 /54 4imes 0/,!6 /54 4)-% /54054 6/,4!'% 0/,"6 /54 $elayed 6 /54 4imes 0/,!6 /54 4)-% /54054 6/,4!'% 0/,"6 /54 $elayed 6 /54 4imes .ot$rawn4o3cale figure 8. coincident or simultaneous phasing (identical slew rates) figure 9. proportional or ratiometric phasing (identical v out time) figure 10. staggered or sequential phasinginclusive (fixed delays) figure 11. staggered or sequential phasingexclusive (fixed cascaded delays) logic systems which are not initialized yet. since both end voltages are differ- ent, each converter reaches its setpoint voltage at a different time. figure 9 shows two pols with different slew rates in order to reach differing ? nal voltages at about the same time.
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 11 of 14 www.cd4power.com 0/,! 0/," 6 ). 6 /54 6 6 /54 6 n6 ). n6 ). 3%142+ 3%142+ !.4) ./)3%&),4%2p&490 -!). 2!-0 2!4% 2 # # 2 2 0/,! 6 ). 6 /54 6 n6 ). 3%142+ 50$. 2 1 # 0/,! 0/," 6 ). 6 /54 6 6 /54 6 n6 ). 3%142+ 3%142+ 2 # 6 ). 6 /54 6 ). n - 7 42)- &%%$"!#+ 3%1 42+ ). 07- #/.42/,,%2 figure 12. wiring for simultaneous phasing figure 13. self-ramping power up figure 14. proportional phasing figure 15. sequence/track simpli? ed equivalent schematic figure 12 shows a basic master (pol a) and slave (pol b) connected so the pol b ramps up identically to pol a as shown in timing diagram, figure 8. rc network r1 and c1 charge up at a rate set by the r1-c1 time constant, giving a roughly linear ramp. as pol a reaches 3.3v out (the setpoint of pol b), pol b will stop rising. pol a then continues rising until it reaches 5v. r1 should be signi? cantly smaller than the internal bias current resistor from the sequence pin. start with a 20k value. we assume that the critical phase is only on power up therefore there is no provision for ramped power down. figure 13 shows a single pol and the same rc network. however, we have added a fet at q1 as an up/down control. when v in power is applied to the pol, q1 is biased on, shorting out the sequence pin. when q1s gate is biased off, r1 charges c1 and the pols output ramps up at the r1-c1 slew rate. note: q1s gate would typically be controlled from some external digital logic. guidelines for sequence/track applications [1] leave the converters on/off enable control (if installed) in the on setting. normally, you should just leave the on/off pin open. [2] allow the converter to stabilize (typically less than 20 ms after +v in power on) before raising the sequence input. also, if you wish to have a ramped power down, leave +v in powered all during the down ramp. do not simply shut off power. [3] if you do not use the sequence/track pin, leave it open or tied to +v in . [4] observe the output slew rate relative to the sequence input. a rough guide is 2 volts per millisecond maximum slew rate. if you exceed this slew rate on the sequence pin, the converter will simply ramp up at its maximum output slew rate (and will not necessarily track the faster sequence input). the reason to carefully consider the slew rate limitation is in case you want two different pols to precisely track each other. if you wish to have a ramped power down (rather than a step down), add a small resistor in series with q1s drain. figure 14 shows both a rc ramp on master pol a and a proportional tracking divider (r2 and r3) on pol b. we have also added an optional very small noise ? lter cap at c2. figure 14s circuit corresponds roughly to figure 9s timing for power up.
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 12 of 14 www.cd4power.com [5] be aware of the input characteristics of the sequence pin. the high input impedance affects the time constant of any small external ramp capacitor. and the bias current will slowly charge up any external caps over time if they are not grounded. the internal pull-up resistor to +v in is typically 400k to 1m . notice in the simpli? ed sequence/track equivalent circuit (figure 15) that a blocking diode effectively disconnects this circuit when the sequence/ track pin is pulled up to +v in or left open. [6] allow the converter to eventually achieve its full-rated setpoint output voltage. do not remain in ramp up/down mode inde? nitely. the converter is characterized and meets all its speci? cations only at the setpoint voltage (plus or minus any trim voltage). during the ramp-up phase, the converter is not considered fully in regulation. this may affect perfor- mance with excessive high current loads at turn-on. [7] the sequence is a sensitive input into the feedback control loop of the converter. avoid noise and long leads on this input. keep all wiring very short. use shielding if necessary. consider adding a small parallel ceramic capacitor across the sequence/track input (see figure 14) to block any external high frequency noise. [8] if one converter is slaving to another master converter, there will be a very short phase lag between the two converters. this can usually be ignored. [9] you may connect two or more sequence inputs in parallel from two converters. be aware of the increasing pull-up bias current and reduced input impedance. [10] any external capacitance added to the converters output may affect ramp up/down times and ramp tracking accuracy. power good output the power good output consists of an unterminated bss138 small signal ? eld effect transistor and a dual window comparator input circuit driving the gate of the fet. power good is true (open drain, high impedance state) if the converters power output voltage is within about 10% of the setpoint. thus, the pg true condition indicates that the converter is approximately within regulation. since an overcurrent condition occurs at about 2% output voltage reduction, the power good does not directly measure an output overcurrent condition at rated maximum output current. however, gross overcurrent or an output short circuit will set power good to false (+0.2v saturation, low impedance condition). using a simple connection to external logic (and returned to the converters common connection), the power good output is unterminated so that the user may adapt the output to a variety of logic families. the pg pin may therefore be used with logic voltages which are not necessarily the same as the input or output power voltages. install an external pullup resistor to the logic supply voltage which is compatible with your logic system. when the power good is out of limit, the fet is at saturation, approximately +0.2v output. keep this low (false) pulldown current to less than 10ma. please note that power good is brie? y false during sequence ramp-up. ignore power good while in transition. "33 () ,/ m! -!8 7indow #omparator %xternal0ullup 2esistor 0/7%2 '//$ 0/7%2 /54054 ()/pen$rain 0ower/+ ,/63aturation 0owernot/+ ,/')# '2/5.$ ,/')# 3500,9 #/--/. 5sers%xternal ,ogic figure 16. equivalent power good circuit
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 13 of 14 www.cd4power.com mechanical specifications case b11 case b12 dimensions are in inches (mm) 2%!26)%7 -aximum ? 4ypical %130 %130 " ! " ! 490 ? 4ypical 2%!26)%7 i/o connections pin function p68 pin function p68 1 +output 6 common 2 +output 7 +input 3 +sense in 8 +input 4 +output b v track /sequence 5 common 9 trim a power good out * 10 on/off control i/o connections pin function p69 1 +output 2v out trim 3 common a vtrack/sequence b power good* 4 +input 5 on/off control * power good output is optional. if not installed, the pin is omitted. * power good output is optional. if not installed, the pin is omitted. 10/16 amp models 6 amp models
? lsn2 series non-isolated, dosa-sip, 6/10/16a selectable-output dc/dc converters lsn2 series page 14 of 14 www.cd4power.com typical performance curves /utput#urrent!mps !mbient4emperature ? # n lfm lfm lfm .atural#onvection ,3. 4 $-aximum#urrent4emperature$erating 6 /54 6airflowfrominputtooutput /utput#urrent!mps !mbient4emperature ? # n lfm .atural#onvection ,3. 4 $-aximum#urrent4emperature$erating 6 /54 6airflowfrominputtooutput ,3. 4 $ %fficiencyvs,ine6oltageand,oad#urrent ?#6 /54 6 ,oad#urrent!mps %fficiency 6 ). 6 6 ). 6 6 ). 6 ,3. 4 $ %fficiencyvs,ine6oltageand,oad#urrent ?#6 /54 6 ,oad#urrent!mps %fficiency 6 ). 6 6 ). 6 6 ). 6 ds-0558 01/06 c&d technologies (datel), inc. makes no representation that the use of its products in the circuits described herein, or the us e of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions co ntained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subject to change without notice. the datel logo is a registered trademark of c&d technologies, inc.. c&d technologies (ncl), ltd. milton keynes, united kingdom, tel: 44 (0) 1908 615232 internet: www.cd4power.com e-mail: ped.ltd@cdtechno.com c&d technologies (datel) s.a.r.l . montigny le bretonneux, france tel: 01-34-60-01-01 internet: www.cd4power.com e-mail: ped.sarl@cdtechno.com c&d technologies (datel) gmbh mnchen, germany tel: 89-544334-0 internet: www.cd4power.com e-mail: ped.gmbh@cdtechno.com c&d technologies kk tokyo, japan tel: 3-3779-1031, osaka tel: 6-6354-2025 int.: www.cd4power.jp email: sales_tokyo@cdtechno.com, sales_osaka@cdtechno.com china shanghai, people's republic of china tel: 86-50273678 internet: www.cd4power.com e-mail: shanghai@cdtechno.com c&d technologies (datel), inc. 11 cabot boulevard, mans? eld, ma 02048-1151 u.s.a. tel: (508) 339-3000 (800) 233-2765 fax: (508) 339-6356 www.cd4power.com email: sales@cdtechno.com iso 9001 registered

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